View ADG1411_2231148.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2 ? max on resistance, 15 v/12 v/5 v i cmos? quad spst switch preliminary technical data ADG1411/adg1412/adg1413 rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 analog devices, inc. all rights reserved. features 2 ? max on resistance 0.5 ? max on resistance flatness 200ma continuous current per channel 33 v supply range fully specified at +12 v, 15 v, 5 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 16-lead tssop and 16-lead lfcsp typical power consumption: <0.03 w applications automatic test equipment data aquisition systems battery-powered systems sample-and-hold systems audio signal routing video signal routing communication systems relay replacement general description the ADG1411/adg1412/adg1413 are monolithic complementary metal-oxide semiconductor (cmos) devices containing four independently selectable switches designed on an i cmos process. i cmos (industrial cmos) is a modular manufacturing process combining high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. functional block diagram in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 ADG1411 switches shown for a logic "1" input in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1412 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1413 figure 1. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. the ADG1411/adg1412/adg1413 contain four independent single-pole/single-throw (spst) switches. the ADG1411 and adg1412 differ only in that the digital control logic is inverted. the ADG1411 switches are turned on with logic 0 on the appropriate control input, while logic 1 is required for the adg1412. the adg1413 has two switches with digital control logic similar to that of the ADG1411; the logic is inverted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. the adg1413 exhibits break-before-make switching action for use in multiplexer applications. inherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. 2 ? ? max on resistance over temperature. 2. minimum distortion 3. 3 v logic-compatible digital inputs: v ih = 2.0 v, v il = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <0.03 w. 6. 16-lead tssop and 4 mm 4 mm lfcsp packages.
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 2 of 17 table of contents specifications..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 6 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configurations and function descriptions ........................... 8 terminology .......................................................................................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 13 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 3 of 17 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. 25c ?40c to +85c ?40c to +125c analog switch analog signal range v dd to v ss v on resistance (r on ) 1.5 ? typ v s = 10 v, i s = ?10 ma; figure 20 2 ? max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels (?r on ) 0.1 ? typ v s = 10 v , i s = ?10 ma 0.5 ? max on resistance flatness (r flat(on) ) 0.1 ? typ v s = ?5 v/0 v/+5 v; i s = ?10 ma 0.5 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.01 na typ v s = 10 v, v d = ? 10 v; figure 21 0.5 2.5 5 na max drain off leakage, i d (off) 0.01 na typ v s = 10v, v d = ? 10 v; figure 21 0.5 2.5 5 na max channel on leakage, i d , i s (on) 0.04 na typ v s = v d = 10 v; figure 22 1 5 5 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 2.5 a typ v in = v inl or v inh 0.5 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 105 ns typ r l = 300 ?, c l = 35 pf 125 185 ns max v s = +10 v; figure 23 t off 40 ns typ r l = 300 ?, c l = 35 pf 50 60 ns max v s = +10 v; figure 23 break-before-make time delay, t d 25 ns typ r l = 300 ?, c l = 35 pf (adg1413 only) 10 ns min v s1 = v s2 = 10 v; figure 24 charge injection 50 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; figure 25 off isolation 50 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 26 channel-to-channel crosstalk 60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 27 total harmonic distortion + noise 0.015 % typ r l = 110 ?, 5 v rms, f = 20 hz to 20 khz ?3 db bandwidth 200 mhz typ r l = 50 ?, c l = 5 pf; figure 28 c s (off) 35 pf typ vs = 0 v, f = 1 mhz c d (off) 35 pf typ vs = 0 v, f = 1 mhz c d , c s (on) 150 pf typ vs = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 220 a typ digital inputs = 5 v
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 4 of 17 25c ?40c to +85c ?40c to +125c 320 a max i ss 0.001 a typ digital inputs = 0 v, 5v or v dd 1. a max v dd /v ss 4.5/16.5 v min/max gnd = 0v 1 guaranteed by design, not subject to production test.
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 5 of 17 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. y version unit test conditions/comments 25c ?40c to +85c ?40c to +125c analog switch analog signal range 0 v to v dd v on resistance (r on ) 2 ? typ v s = +10 v, i s = ?10 ma; figure 20 3 4 ? max v dd = +10.8 v, v ss = 0 v on resistance match between channels (?r on ) 0.1 ? typ v s = +10 v, i s = ?10 ma ? max on resistance flatness (r flat(on) ) 0.1 ? typ v s = ?5 v/0 v/+5 v, i s = ?10 ma leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/0 v; figure 21 0.5 2.5 5 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/0 v; figure 21 0.5 2.5 5 na max channel on leakage, i d , i s (on) 0.04 na typ v s = v d = 1 v or 10 v; figure 22 1 5 5 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.5 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 120 ns typ r l = 300 ?, c l = 35 pf 155 225 ns max v s = 8 v; figure 23 t off 45 ns typ r l = 300 ?, c l = 35 pf 65 85 ns max v s = 8 v; figure 23 break-before-make time delay, t d 50 ns typ r l = 300 ?, c l = 35 pf (adg1413 only) 10 ns min v s1 = v s2 = 8 v; figure 24 charge injection 50 pc typ v s = 6 v, r s = 0 ?, c l = 1 nf; figure 25 off isolation 50 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 26 channel-to-channel crosstalk 60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 27 total harmonic distortion + noise 0.015 % typ r l = 110 ?, 5 v rms, f = 20 hz to 20 khz ?3 db bandwidth 200 mhz typ r l = 50 ?, c l = 5 pf; figure 28 c s (off) 35 pf typ vs = 6v, f = 1 mhz c d (off) 35 pf typ vs = 6v, f = 1 mhz c d , c s (on) 150 pf typ vs = 6v, f = 1 mhz power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 220 a typ digital inputs = 5 v 320 a max v dd 5/16.5 v min/max gnd = 0v, vss = 0v 1 guaranteed by design, not subject to production test.
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 6 of 17 dual supply v dd = 5 v 10%, v ss = -5 v 10%, gnd = 0 v, unless otherwise noted. table 3. 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 3 ? typ v s = 3.3v, i s = ?10 ma; figure 20 4 ? max v dd = +4.5 v, v ss = ?4.5 v on resistance match between channels (?r on ) 0.1 ? typ v s = 3.3 v , i s = ?10 ma ? max on resistance flatness (r flat(on) ) 0.1 ? typ v s = ?3 v/0 v/+3 v; i s = ?10 ma leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off) 0.01 na typ v s = 4.5 v, v d = ? 4.5 v; figure 21 0.5 2.5 5 na max drain off leakage, i d (off) 0.01 na typ v s = 4.5v, v d = ? 4.5 v; figure 21 0.5 2.5 5 na max channel on leakage, i d , i s (on) 0.04 na typ v s = v d = 4.5v; figure 22 1 5 5 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0.5 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 120 ns typ r l = 300 ?, c l = 35 pf 155 225 ns max v s = 3 v; figure 23 t off 45 ns typ r l = 300 ?, c l = 35 pf 65 85 ns max v s = 3 v; figure 23 break-before-make time delay, t d 50 ns typ r l = 300 ?, c l = 35 pf (adg1413 only) 10 ns min v s1 = v s2 = 8 v; figure 24 charge injection 10 pc typ v s = 0v, r s = 0 ?, c l = 1 nf; figure 25 off isolation 50 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 26 channel-to-channel crosstalk 60 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; figure 27 total harmonic distortion + noise 0.015 % typ r l = 110 ?, 5 v rms, f = 20 hz to 20 khz ?3 db bandwidth 200 mhz typ r l = 50 ?, c l = 5 pf; figure 28 c s (off) 35 pf typ vs = 0v, f = 1 mhz c d (off) 35 pf typ vs = 0v, f = 1 mhz c d , c s (on) 150 pf typ vs = 0v, f = 1 mhz power requirements v dd = 5.5 v , vss = -5.5v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 5 v 1.0 a max v dd /v ss 4.5/16.5 v min/max gnd = 0v 1 guaranteed by design, not subject to production test.
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 7 of 17 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss C 0.3 v to v dd + 0.3 v digital inputs 1 gnd C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 300 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d 200 ma operating temperature range automotive (y versio n) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance 150.4c/w 16-lead lfcsp, ja thermal impedance 72.7c/w reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 8 of 17 pin configurations and function descriptions

figure 2. tssop pin configuration ADG1411 adg1412 adg1413 top view (not to scale) 11 9 8 7 6 5 4 3 2 1 12 13 14 15 16 10 d4 vss s3 s4 s1 s2 in4 d1 nc vdd gnd in3 d3 in1 in2 d2 exposed pad tied to substrate, vss nc = no connect figure 3. lfcsp pin configuration table 5. pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 in1 logic control input. 2 16 d1 drain terminal. can be an input or output. 3 1 s1 source terminal. can be an input or output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal. can be an input or output. 7 5 d4 drain terminal. can be an input or output. 8 6 in4 logic control input. 9 7 in3 logic control input. 10 8 d3 drain terminal. can be an input or output. 11 9 s3 source terminal. can be an input or output. 12 10 nc no connection. 13 11 v dd most positive power supply potential. 14 12 s2 source terminal. can be an input or output. 15 13 d2 drain terminal. can be an input or output. 16 14 in2 logic control input. table 6. ADG1411/adg1412 truth table ADG1411 inx adg1412 inx switch condition 0 1 on 1 0 off table 7. adg1413 truth table logic - inx switch 1, 4 switch 2, 3 0 off on 1 on off
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 9 of 17 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminals d and s. r on the ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, measured with reference to ground. c d (off) the off switch drain capacitance, measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and the output switching on. see figure 23. t off the delay between applying the digital control input and the output switching off. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n the ratio of the harmonic amplitude plus noise of the signal to the fundamental.
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 10 of 17 typical performance characteristics figure 4. on resistance as a function of v d (v s ) for dual supply figure 5. on resistance as a function of v d (v s ) for single supply figure 6. on resistance as a function of v d (v s ) for different temperatures, dual supply figure 7. on resistance as a function of v d (v s ) for different temperatures, single supply figure 8. leakage currents as a function of temperature, dual supply figure 9. leakage currents as a function of temperature, single supply
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 11 of 17 figure 10. logic threshold voltage vs. supply voltage figure 11. i dd vs. logic level figure 12. charge injection vs. source voltage figure 13. t on /t off times vs. temperature figure 14. off isolation vs. frequency figure 15. crosstalk vs. frequency
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 12 of 17 figure 16. on response vs. frequency figure 17. capacitance vs. source voltage, dual supply figure 18. capacitance vs. source voltage, single supply figure 19. thd + n vs. frequency
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 13 of 17 test circuits i ds v1 sd v s r on = v1/i ds 04778-0-020 sd v s a a v d i s (off) i d (off) 04778-0-021 sd a v d i d (on) nc nc = no connect 04778-0-022 figure 20. on resistance figure 21. off leakage figure 22. on leakage v s in sd gnd r l 300v c l 35pf v out v dd v ss 0.1 f v dd 0.1 f v ss adg1211 adg1212 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 04778-0-023 figure 23. switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300v c l 35pf v out2 v out1 v dd v ss 0.1 f v dd 0.1 f v ss v in v out1 v out2 adg1213 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300v c l 35pf 04778-0-024 figure 24. break-before-make time delay in v out adg1212 adg1211 v in v in v out off dv out on q inj = c l 3 dv out sd v dd v ss v dd v ss v s r s gnd c l 1nf 04778-0-025 figure 25. charge injection
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 14 of 17 v out 50 ? network analyzer r l 50 ? in v in s d 50 ? off isolation = 20 log v out v s v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 04778-0-026 figure 26. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 ? r 50 ? v s v s v dd v ss 0.1 f v dd 0.1 f v ss 04778-0-027 figure 27. channel-to-channel crosstalk v out 50 ? network analyzer r l 50 ? in v in s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 04778-0-028 figure 28. bandwidth v out r s audio precision r l 600 ? in v in s d v s v p-p v dd v ss 0.1 f v dd 0.1 f v ss gnd 04779-0-030 figure 29.. thd + noise
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 15 of 17 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab figure 29. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicato r top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 exposed pad (bottom view) compliant to jedec standards mo-220-vggc 12 max 1.00 0.85 0.80 seating plane 0.30 0.23 0.18 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.75 0.60 0.50 0.25 min 2.25 2.10 sq 1.95 figure 30. 16-lead lead frame chip scale package [vq_lfcsp] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters
ADG1411/adg1412/adg1413 preliminary technical data rev. pre | page 16 of 17 ordering guide model temperature range package description package option ADG1411yruz 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 ADG1411yruz-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 ADG1411yruz-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 ADG1411ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 ADG1411ycpz-reel7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 adg1412yruz 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1412yruz-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1412yruz-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1412ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 adg1412ycpz-reel7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 adg1413yruz 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1413yruz-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1413yruz-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1413ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 adg1413ycpz-reel7 1 ?40c to +125c lead frame chip scale package (vq_lfcsp) cp-16-4 1 z = pb-free part.
preliminary technical data ADG1411/adg1412/adg1413 rev. pre | page 17 of 17 notes ? 2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06615-0-5/07(pre)

▲Up To Search▲

Price & Availability of ADG1411

	To Download ADG1411 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .